ASIC Design Technical Leader - Design & Timing Constraints Focus

Company: Cisco Systems, Inc.
Location: San Jose
Posted on: May 3, 2025

Job Description:

The application window is expected to close on: US 5/30/2025This position will be onsite in San Jose 5 days per week
Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and cafe, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also have an opportunity to work with other ASIC teams in the journey of taking it from concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and Back-end teams to understand chip architecture and guide them in refining design and timing constraints for seamless physical design closure. As part of this team, you'll contribute to developing next-generation networking chips. Responsibilities include:

• Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
• Option to also do block level RTL design or block or top-level IP integration.
• Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
• Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
• Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
• Creating fullchip clocking diagrams and related documentation. Minimum Qualifications:
  • Bachelor's Degree in Electrical or Computer Engineering with 8+ years of ASIC or related experience or Master's Degree in Electrical or Computer Engineering with 6+ years of ASIC or related experience
  • Experience with block/full chip SDC development in functional and test modes.
  • Experience in Static Timing Analysis and prior working experience with STA tools like PrimeTime/Tempus
  • Understanding of related digital design concepts (eg. clocking and async boundaries)
  • Experience with synthesis tools (eg. Synopsys DC/DCG/FC), Verilog/System Verilog programming Preferred Qualifications:
    • Experience with constraint analyzer tools such as TCM (Timing Constraint Manager from Synopsys) and CCD (Conformal Constraint Designer from Cadence)
    • Experience with Spyglass CDC and glitch analysis
    • Experience using Formal Verification: Synopsys Formality and Cadence LEC.
    • Experience with scripting languages such as Python, Perl, or TCL
      #WeAreCisco #WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best. We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do!Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!
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Keywords: Cisco Systems, Inc., Watsonville , ASIC Design Technical Leader - Design & Timing Constraints Focus, IT / Software / Systems , San Jose, California